Having 14+ year experience in ASIC/FPGA design in both IP and SoC. Have worked in different USB versions: USB2.0, 3.1/3.2 in device controlled Host and Hub functionalities design. Having worked different ASIC flow stages in the front end, including design, micro architecture, integration and IP validation, including CDC, RDC, synthesis, functional simulation verification, Lint, LEC and documentation.
Bachelor of Engineering in Electrical and Electronics Engineering,
Diploma in VLSI design.
ASIC design, FPGA design, IP Logic design, Digital design.
Having USB, AXI. AHB protocol experiences,
Having experiences in CDC, RDC validation
reading books,
reading techincal magazines
Watching news
playing cricket, Chess, foot ball games
watching news and games
playing with kids
cooking with different dishes
